1. Field of the Invention
The present invention relates to data handling in general and more particularly to a synchronizer which synchronizes data with clock pulses.
2. Prior Art
In designing synchronous digital systems, there are times when it is required to pass data unidirectionally between two groups of logic. Oftentimes, the clocks for the two groups of logic are different. Before the receiving logic can use the data, the data must be resynchronized with the clocks of the receiving logic. A typical or straigntforward solution is to design a set of "handshaking" signals between the two groups of logics. The handshaking signals are used to indicate the arrival and acceptance of data. The typical solution requires multiple clock cycles (source and sink) per synchronized data item. The solution causes a throughput "bottleneck" at the synchronizer. Systems in which a data item can be processed every clock cycle are susceptible to the throughput "bottleneck" error condition.
Another prior art solution to the above problem is set fourth in U.S. Pat. No. 4,119,796. In the patent a digital phase lock loop synchronizes an incoming clock with a local clock. A shift register delays incoming data pulses by the same amount as the incoming clock pulses so that the data pulses are synchronized with the local clock. An output of a counter is used to drive a selector that selects the proper output of the shift register.
Still other prior art solutions are described in U.S. Pat. Nos. 4,065,862 and 4,320,515. Both patents require the use of shift registers through which the data to be synchronized is shifted. Phase lock loops are used to generate internal clocks. The frequencies of the generated clocks are usually higher than the frequencies of the source and/or sink clocks.